General purpose digital computers are constructed to perform a wide variety of functions. Being so constructed, such general purpose computers may be limited in the speed with which they can perform certain specific computations. Where the specific computation is both complex and to be performed repeatedly on different sets of data, the problem of speed limitation may become significant. One solution to achieving an increase in the speed of performance is to construct a high speed computing device uniquely adapted to perform the particular computation. Typically, the high speed device receives operating instructions and data from a general purpose, host computer by way of a controller. As is well known in the art, the controller functions to process complex, high level macro-instructions issued by the host computer and provide the high speed device with a sequence of microcode instructions and data. The controller in performing this function receives the macro-instructions at a relatively slow rate and provides to the high speed device the microcode instructions at a much higher rate. In such a system, the host computer is free of the task of performing the computation performed by the high speed device and may therefore spend the available time on other tasks.
One example of a computing system as described above is one in which the high speed device comprises a parallel array of processors receiving microcode in the single instruction multiple data (SIMD) format. In such a system, the host provides high level macro-instructions to the controller at a relatively low rate, e.g., 1 MHz. The controller, in response to each macro-instruction, provides a sequence of microcode instructions which, in SIMD format, is applied to the processors in the array at a relatively high rate, e.g., 10 MHz.
A second example is a computing system having one or more special purpose (SP) processors attached to a host computer through a controller. The SP processors, which may differ from one another or be identical, are each adapted to solve a portion of a specific type of problem. The SP processors may be configured both in parallel and in series respectively according to what portions of the problem may be solved simultaneously and what portions require a result from solving a previous portion. As in the case of the parallel processor array, the controller in the attached SP processor system receives macro-instructions from the host at a relatively low rate and provides microcode to the attached processors at a higher rate, the exemplary rates noted above also being applicable to such a system.
A primary design objective in such systems is to maximize the operating efficiency of the high speed device. This operating efficiency is degraded by any inability of the controller to provide a continuous sequence of microcode instructions to the high speed device. In such cases where the controller is unable to provide a microcode instruction on any instruction cycle, the controller issues a no-op instruction, i.e. it tells the high speed device to do nothing on that cycle. Thus, operating inefficiency may be measured by the ratio of no-op's to valid microcode instructions.
Primary causes of no-op instructions in such systems are CALL and INTERRUPT instruction routines, whether originated by the host computer, the high speed device or the controller itself. In response to either a CALL or INTERRUPT, the controller, and hence the high speed device, suspends the current sequence of instructions and initiates a new sequence in its place. Before this can be accomplished, however, the contents of the controller's program counter must be saved as must the information present in the controller, i.e. state of the system, upon receipt of the INTERRUPT or CALL. The saving of this information is required so it can be recalled when a RETURN instruction is later provided, thereby enabling the controller and high speed device to return to where they left off in the interrupted instruction sequence. This saving of information and its later recall require multiple instruction cycles for which no-op instructions must be issued to the high speed device.
The program counter is typically a discrete device in the controller and one or more instruction cycles are required to save its current value by pushing it onto stack memory or transferring it to random access memory (RAM). Subsequently, additional instruction cycles are required to transfer the computational results representative of the system state, at the time of interrupt, to available RAM. The RETURN instruction routine requires further instruction cycles to perform these functions in reverse. As stated above, no-op's must be provided to the high speed device during these instruction cycles. As a result, system operating efficiency is significantly degraded.
It is further noted that in order to perform the functions described above, the controller includes a plurality of different devices to serve different functions, e.g. a program counter, memory space, and a memory controller. Provision of this many different devices serves to increase the cost of the controller. Further, since the devices are physically different, it is more difficult to perform parallel operations with them. Examples of different devices to serve some of the above described functions are the Ser. No. 74890 sequencer and the Ser. No. 74888 register-ALU slice, both provided by the Texas Instruments Company.
It, therefore is an object of the present invention to provide a device, for use in a computing system, which enables minimization of the number of instruction cycles to save the program counter and system state.